ADC3_VCM_RDIV_EN=Val_0x0, ADC3_TEST_EN=Val_0x0, ADC2_COMPARATOR_EN=Val_0x0, ADC2_DIFFERENTIAL_EN=Val_0x0, ADC2_VCM_RDIV_EN=Val_0x0, ADC2_COMPARATOR_BIAS=Val_0x0, ADC2_TEST_EN=Val_0x0, ADC1_VCM_RDIV_EN=Val_0x0, ADC1_DIFFERENTIAL_EN=Val_0x0, ADC3_COMPARATOR_EN=Val_0x0, ADC1_COMPARATOR_EN=Val_0x0, ADC3_DIFFERENTIAL_EN=Val_0x0, ADC3_COMPARATOR_BIAS=Val_0x0, ADC1_TEST_EN=Val_0x0, ADC1_COMPARATOR_BIAS=Val_0x0
ADC Analog Control Register for ADC12 Modules
| ADC1_TEST_EN | Enable ADC120 test signal to go to the test MUX: 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| ADC1_DIFFERENTIAL_EN | Enable ADC120 differential mode: 0 (Val_0x0): IN0, IN1, IN2, IN3, IN4, and IN5 are single-ended inputs 1 (Val_0x1): IN0/IN1, IN2/IN3, and IN4/IN5 make 3 differential inputs |
| ADC1_COMPARATOR_EN | Enable ADC120 comparator: 0 (Val_0x0): Comparator is off 1 (Val_0x1): Comparator is enabled |
| ADC1_COMPARATOR_BIAS | ADC120 comparator biasing: 0 (Val_0x0): 0.5 MS/s 1 (Val_0x1): 1 MS/s 2 (Val_0x2): 2.5 MS/s 3 (Val_0x3): 5 MS/s |
| ADC1_VCM_RDIV_EN | Enable ADC120 resistive divider: 0 (Val_0x0): The resistive divider is off, common mode is not well defined 1 (Val_0x1): The resistive divider is on, common mode is VDD/2 |
| ADC2_TEST_EN | Enable ADC121 test signal to go to the test MUX: 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| ADC2_DIFFERENTIAL_EN | Enable ADC121 differential mode: 0 (Val_0x0): IN0, IN1, IN2, IN3, IN4, and IN5 are single-ended inputs 1 (Val_0x1): IN0/IN1, IN2/IN3, and IN4/IN5 make 3 differential inputs |
| ADC2_COMPARATOR_EN | Enable ADC121 comparator: 0 (Val_0x0): Comparator is off 1 (Val_0x1): Comparator is enabled |
| ADC2_COMPARATOR_BIAS | ADC121 comparator biasing: 0 (Val_0x0): 0.5 MS/s 1 (Val_0x1): 1 MS/s 2 (Val_0x2): 2.5 MS/s 3 (Val_0x3): 5 MS/s |
| ADC2_VCM_RDIV_EN | Enable ADC121 resistive divider: 0 (Val_0x0): The resistive divider is off, common mode is not well defined 1 (Val_0x1): The resistive divider is on, common mode is VDD/2 |
| ADC3_TEST_EN | Enable ADC122 test signal to go to the test MUX: 0 (Val_0x0): Disabled 1 (Val_0x1): Enabled |
| ADC3_DIFFERENTIAL_EN | Enable ADC122 differential mode: 0 (Val_0x0): IN0, IN1, IN2, IN3, IN4, and IN5 are single-ended inputs 1 (Val_0x1): IN0/IN1, IN2/IN3, and IN4/IN5 make 3 differential inputs |
| ADC3_COMPARATOR_EN | Enable ADC122 comparator: 0 (Val_0x0): Comparator is off 1 (Val_0x1): Comparator is enabled |
| ADC3_COMPARATOR_BIAS | ADC122 comparator biasing: 0 (Val_0x0): 0.5 MS/s 1 (Val_0x1): 1 MS/s 2 (Val_0x2): 2.5 MS/s 3 (Val_0x3): 5 MS/s |
| ADC3_VCM_RDIV_EN | Enable ADC122 resistive divider: 0 (Val_0x0): The resistive divider is off, common mode is not well defined 1 (Val_0x1): The resistive divider is on, common mode is VDD/2 |
| AMUX_CONT | Analog test mux control (external to ADC12). Bit 31 is a master enable (set to 1 to enable AMUX). Upper 4 bits determine mux section [30:27]. Lower 3 bits select mux input [26:24]. Default = 0x0 |